1. Field of the Invention
The present invention relates to a clock recovery circuit, and more particularly, to an over-sampling type clock recovery circuit which performs sampling of a data signal based on a plurality of clock signals having different phases.
2. Description of the Related Art
In recent years, a high-speed protocol has been proposed such as Gbit Ethernet and Fiber Channel for data transmission. For this purpose, high speed processing is requested in a clock recovery circuit to extract a clock signal from a data signal in a high speed transmission and in a PLL circuit to establish frequency synchronization between the clock signal used in the circuit and the transmitted clock signal. In order to respond to such a request, as disclosed in 1996 IEEE International Solid-State Circuits Conference, an over-sampling type clock recovery circuit has been proposed in which the transmitted data signal is sampled based on a plurality of clock signals with different phases generated by an internal circuit.
FIG. 1 shows a circuit block diagram of a clock recovery circuit which is disclosed in the conventional example. A data signal is supplied to eight phase comparators TIPD0 to TIPD7. The respective phase comparators TIPD0 to TIPD7 are supplied with 24 clock signals having fixed delays outputted from a fixed delay circuit for every set of three clock signals. Each phase comparator detects the phase state between the data signal and the set of three clock signals. When the set of clock signals leads the data signal; the phase comparator detects the leading of the clock signals to set a corresponding one of dn signals dn0 to dn7 to an enable state and a corresponding one of up signals up0 to up7 to a disable state. Similarly, when detecting the delay of the clock signal than the data signal, the phase comparator sets the dn signal to the disable state and the up signal to the enable state.
Charge pumps CP0 to CP7 increase the output voltages when the up signals are set to the enable state and decrease the output voltages decrease when the dn signal is set to the enable state. The output voltages are supplied to a low pass filter LPF. The low pass filter LPF integrates the changes of these voltages and outputs the integrated voltage to a variable delay circuit VD. A voltage controlled oscillator VCO oscillates and generates a basic clock signal to output to the variable delay circuit VD. The variable delay circuit VD delays the basic clock signal from the voltage controlled oscillator VCO in accordance with the integrated voltage from the low pass filter LPF. Then, a fixed delay circuit FD receives the delayed clock signal from the variable delay circuit FD and generates the 24 clock signals having fixed delays from the delayed clock signal.
In the clock recovery circuit, the up signal or dn signal is set to the enable state in each phase comparator. As a result, the voltage outputted from the corresponding charge pump CP increases or decreases, when the leading or delaying states of the set of clock signals is detected. Therefore, the delayed clock signal is outputted from the variable delay circuit VD based on the phase leading or delaying state, and the 24 clock signals are generated by the fixed delay circuit FD based on the delayed clock signal. As a result, the leading or delaying state of the clock signals to be supplied to each of the phase comparators TIPD0 to TIPD7 is controlled so that the appropriate sampling of the data signal can be realized.
In such a clock recovery circuit, the number of bits of the transmitted data signal continuously having the same value is limited. Therefore, in a locking state in which any phase difference is not detected, even if the number of clock signals used for the sampling is decreased, the phase difference can be correctly detected.
However, in the above-mentioned clock recovery circuit, the eight phase comparators TIPD0 to TIPD7 are always in the operating state regardless of whether or not they are in the locking state. As the result, in the locking state, phase comparators other than those necessary to detect phase differences perform unnecessary operations. Therefore, the eight phase comparators with the relatively large power consumption operate continuously at the same time. Thus, the power consumption as the whole clock recovery circuit cannot be ignored. Also, each of the charge pumps CP0 to CP7 subsequent to the phase comparators TIPD0 to TIPD7 operate based on phase difference data outputted from the respective phase comparators. Moreover, the power consumption in the low pass filter LPF and the subsequent circuits cannot be ignored.
In addition to the above conventional example, a transmission path signal receiving system is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 3-92033). In this reference, the transmission path signal receiving system includes a signal converting section, a reference clock generating section, a determining section, and clock reproducing section. The signal converting section converts the transmission path signal into a logic signal. The reference clock generating section generates a reference clock signal having a frequency higher than a bit rate of a digital data of the transmission path signal. The determining section performs over-sampling and a logic process to the logic signal using the reference clock signal and determines a value of the digital data. The clock reproducing section inserts a predetermined pulse into the logic signal in accordance with the determining result of the determining section to reproduce a clock signal.
Also, a data receiving apparatus is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 8-317007). In this reference, the data receiving apparatus includes an A/D converting section 24, an adding section 25, a detecting section 26, a demodulating section 27, a detecting section 28, variable frequency dividing section 30, a control section 29, frame, sync signals generating sections 31 and 32. The A/D converting section 24 performs over-sampling of a reception signal based on a free-running clock signal having a frequency of integer times of a symbol rate to convert the sampling values into digital values. The adding section 25 adding the digital sampling values synchronously for a symbol period over a predetermined period. The detecting section 26 detects a symbol identifying point from the synchronously adding result. The demodulating section 27 performs data demodulation based on the sample value at the symbol identifying point. The detecting section 28 detects the displacement of the symbol identifying point accompanied with time as a phase shift. The variable frequency dividing section 30 divides the free-running clock signal in frequency to reproduce a bit clock signal. The control section 29 controls a frequency division ratio of the variable frequency dividing section 30 to correct a phase shift. The frame sync signals generating sections 31 and 32 extract a known sync word from the demodulated data to establish a frame synchronization and generate a frame sync timing signal based on the extracted sync word.